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ds05-20860-3e fujitsu semiconductor data sheet flash memory cmos 8m (1m 8/512k 16) bit mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 n features ? single 3.0 v read, program, and erase minimizes system level power requirements ? simultaneous operations read-while-erase or read-while-program ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts (pin compatible with mbm29lv800ta/ba) 48-pin tsop(i) (package suffix: pftn C normal bend type, pftr C reversed bend type) 48-ball fbga (package suffix: pbt) ? minimum 100,000 program/erase cycles ? high performance 70 ns maximum access time ? sector erase architecture two 16k byte, four 8k bytes, two 32k byte, and fourteen 64k bytes. any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device (continued) embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 2 (continued) ? sector protection hardware method disables any combination of sectors from program or erase operations ? sector protection set function by extended sector protection command ? fast programming function by extended command ? temporary sector unprotection temporary sector unprotection via the reset pin. n pac k ag e 48-pin plastic tsop (i) (fpt-48p-m19) 48-pin plastic tsop (i) (fpt-48p-m20) marking side marking side 48-pin plastic fbga (bga-48p-m02) (bga-48p-m12)
3 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 n general description the mbm29dl800ta/ba are a 8m-bit, 3.0 v-only flash memory organized as 1m bytes of 8 bits each or 512k words of 16 bits each. the mbm29dl800ta/ba are offered in a 48-pin tsop(i) and 48-ball fbga packages. these devices are designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. mbm29dl800ta/ba provides simultaneous operation which can read a data while program/erase. the simultaneous operation architecture provides simultaneous operation by dividing the memory space into two banks. the device can allow a host system to program or erase in one bank, then immediately and simultaneously read from the other bank. the standard mbm29dl800ta/ba offer access times 70 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29dl800ta/ba are pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29dl800ta/ba are programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the devices automatically time the erase pulse widths and verify proper cell margin. a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the devices also feature a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29dl800ta/ba are erased when shipped from the factory. the devices feature single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. fujitsus flash technology combines years of eprom and e2prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29dl800ta/ba memories electrically erase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 4 n flexible sector-erase architecture ? two 16k bytes, four 8k bytes, two 32k bytes, and fourteen 64k bytes ? individual-sector, multiple-sector, or bulk-erase capability ? individual or multiple-sector protection is user definable. 16k byte 8k byte 8k byte 32k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 7ffffh 7dfffh 7cfffh 7bfffh 77fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 07fffh 00000h fffffh fbfffh f9fffh f7fffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 00000h 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 64k byte 32k byte 8k byte 8k byte 16k byte fffffh effffh dffffh cffffh bffffh affffh 9ffffh 8ffffh 7ffffh 6ffffh 5ffffh 4ffffh 3ffffh 2ffffh 1ffffh 0ffffh 07fffh 05fffh 03fffh 00000h 7ffffh 77fffh 6ffffh 67fffh 5ffffh 57fffh 4ffffh 47fffh 3ffffh 37fffh 2ffffh 27fffh 1ffffh 17fffh 0ffffh 07fffh 03fffh 02fffh 01fffh 00000h mbm29lv800ta sector architecture mbm29lv800ba sector architecture ( 16) ( 8) ( 16) ( 8)
5 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 n product line up n block diagram part no. mbm29dl800ta/mbm29dl800ba ordering part no. v cc = 3.3 v +0.3 v C0.3 v -70 v cc = 3.0 v +0.6 v C0.3 v -90-12 max. address access time (ns) 70 90 120 max. ce access time (ns) 70 90 120 max. oe access time (ns) 30 35 50 v ss v cc we ce a 0 to a 18 oe erase voltage generator dq 0 to dq 15 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb timer for program/erase a -1 byte reset ry/by buffer ry/by
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 6 n connection diagrams a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 n.c. n.c. we reset n.c. n.c. ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mbm29lv800ta/mbm29lv800ba standard pinout mbm29lv800ta/mbm29lv800ba reverse pinout tsop(i) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 reset we a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc sop (top view) a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by n.c. n.c. reset we n.c. n.c. a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 (marking side) (marking side) fpt-44p-m16 fpt-48p-m19 fpt-48p-m20
7 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 (continued) a3 a1 a2 a6 a5 b1 b2 b3 b4 b5 b6 c1 c2 c3 c4 c5 c6 d1 d2 d3 d4 d5 d6 e1 e2 e3 e4 e5 e6 f1 f2 f3 f4 f5 f6 g1 g2 g3 g4 g5 g6 h1 h2 h3 h4 h5 h6 (top view) marking side bga-48p-m02 fbga a4 a1 a 3 a2 a 7 a3 ry/by a4 we a5 a 9 a6 a 13 b1 a 4 b2 a 17 b3 n.c. b4 reset b5 a 8 b6 a 12 c1 a 2 c2 a 6 c3 a 18 c4 n.c. c5 a 10 c6 a 14 d1 a 1 d2 a 5 d3 n.c. d4 n.c. d5 a 11 d6 a 15 e1 a 0 e2 dq 0 e3 dq 2 e4 dq 5 e5 dq 7 e6 a 16 f1 ce f2 dq 8 f3 dq 10 f4 dq 12 f5 dq 14 f6 byte g1 oe g2 dq 9 g3 dq 11 g4 v cc g5 dq 13 g6 dq 15 /a -1 h1 v ss h2 dq 1 h3 dq 3 h4 dq 4 h5 dq 6 h6 v ss bga-48p-m12
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 8 n logic symbol table 1 mbm29dl800ta/ba pin configuration pin function a -1 , a 0 to a 18 address inputs dq 0 to dq 15 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector unprotection byte selects 8-bit or 16-bit mode n.c. no internal connection v ss device ground v cc device power supply 19 a 0 to a 18 we oe ce dq 0 to dq 15 16 or 8 byte reset a -1 ry/by
9 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. see table 8. 2. refer to the section on sector protection. 3. we can be v il if oe is v il , oe at v ih initiates the write operations. 4. v cc = 3.0 v 10% 5. it is also used for the extended sector protection. table 2 mbm29dl800ta/ba user bus operations (byte = v ih ) operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 reset auto-select manufacturer code (1) l l h l l l v id code h auto-select device code (1) l l h h l l v id code h read (3) l l h a 0 a 1 a 6 a 9 d out h standby hxxxxxx high-z h output disable lhhxxxx high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 d in h enable sector protection (2), (4) l v id lhlv id xh verify sector protection (2), (4) l l h l h l v id code h temporary sector unprotection (5) xxxxxxx x v id reset (hardware)/standby xxxxxxx high-z l table 3 mbm29dl800ta/ba user bus operations (byte = v il ) operation ce oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 0 to dq 7 reset auto-select manufacturer code (1) l l h l l l l v id code h auto-select device code (1) l l h l h l l v id code h read (3) l l h a -1 a 0 a 1 a 6 a 9 d out h standby h x x x xxxxhigh-z h output disable lhhxxxxxhigh-z h write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in h enable sector protection (2), (4) l v id llhlv id xh verify sector protection (2), (4) l l h l l h l v id code h temporary sector unprotection (5)xxxxxxxx x v id reset (hardware)/standby xxxxxxxxhigh-z l
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 10 n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29dl800 t a -70 pftn device number/description mbm29dl800 8mega-bit (1m 8-bit or 512k 16-bit) cmos flash memory 3.0 v-only read, program, and erase pa c k a g e t y p e pftn = 48-pin thin small outline package (tsop) standard pinout pftr = 48-pin thin small outline package (tsop) reverse pinout pbt = 48-ball fine pitch ball grid array package (fbga:bga-48p-m02) pbt-sf2 =48-ball fine pitch ball grid array package (fbga:bga-48p-m12) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector
11 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 n functional description simultaneous operation mbm29dl800ta/ba have feature, which is capability of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). the bank selection can be selected by bank address (a 16 to a 18 ) with zero latency. the mbm29dl800ta/ba have two banks which contain bank 1 (16kb, 32kb, 8kb, 8kb, 8kb, 8kb, 32kb, and 16kb) and bank 2 (64kb fourteen sectors). the simultaneous operation can not execute multi-function mode in the same bank. table 4 shows combination to be possible for simultaneous operation. *: an erase operation may also be supended to read from or program to a sector not being erased. read mode the mbm29dl800ta/ba have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h or l standby mode there are two ways to implement the standby mode on the mbm29dl800ta/ba devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current is consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. table 4 simultaneous operation case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 12 automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29dl800ta/ba data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to activate this mode, mbm29dl800ta/ba automatically switch themselves to low power mode when mbm29dl800ta/ba addresses remain stably during access fine of 300 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level). during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically and mbm29dl800ta/ba read-out the data for changed addresses. output disable with the oe input at a logic high level (v ih ), output from the devices are disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 (a -1 ). (see tables 2 and 3.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29dl800ta/ba are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 8. (refer to autoselect command section.) word 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and word 1 (a 0 = v ih ) represents the device identifier code (mbm29dl800ta = 4ah and mbm29dl800ba = cbh for 8 mode; mbm29dl800ta = 224ah and mbm29dl800ba = 22cbh for 16 mode). these two bytes/words are given in the tables 5.1 and 5.2. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see tables 5.1 and 5.2.) in case of applying v id on a 9 , since both bank 1 and bank 2 enters autoselect mode, the simultenous operation can not be executed.
13 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 *1: a -1 is for byte mode. *2: outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. (b): byte mode (w): word mode table 5 .1 mbm29dl800ta/ba sector protection verify autoselect codes type a 12 to a 18 a 6 a 1 a 0 a -1 *1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29dl800ta byte xv il v il v ih v il 4ah word x 224ah mbm29dl800ba byte xv il v il v ih v il cbh word x 22cbh sector protection sector addresses v il v ih v il v il 01h *2 table 5 .2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0 000000000 000100 device code mbm29dl800ta (b) 4ah a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01001010 (w) 224ah 0010001001 001010 mbm29dl800ba (b) cbh a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 11001011 (w) 22cbh 0010001011 001011 sector protection 01h a -1 /0 000000000 000001
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 14 write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29dl800ta/ba feature hardware sector protection. this feature will disable both program and erase operations in any number of sectors (0 through 21). the sector protection feature is enabled using programming equipment at the users site. the devices are shipped with all sectors unprotected. alternatively, fujitsu may program and protect sectors in the factory prior to shiping the device. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il , and a 0 = a 6 = v il , a 1 = v ih . the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. tables 6 and 7 define the sector address for each of the twenty two (22) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see figures 16 and 25 for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the devices will read 00h for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to apply to v il on byte mode. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector address will produce a logical 1 at dq 0 for a protected sector. see tables 5.1 and 5.2 for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previously protected sectors of the mbm29dl800ta/ba devices in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously protected sectors will be protected again. see figures 17 and 26.
15 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 reset hardware reset the mbm29dl800ta/ba devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see figure 12 for the timing diagram. refer to temporary sector unprotection for additional functionality.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 16 note: the address range is a 18 : a -1 if in byte mode (byte = v il ). the address range is a 18 : a 0 if in word mode (byte = v ih ). table 6 sector address tables (mbm29dl800ta) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa0 0000xxx 64/32 00000h to 0ffffh 00000h to 07fffh sa1 0001xxx 64/32 10000h to 1ffffh 08000h to 0ffffh sa2 0010xxx 64/32 20000h to 2ffffh 10000h to 17fffh sa3 0011xxx 64/32 30000h to 3ffffh 18000h to 1ffffh sa4 0100xxx 64/32 40000h to 4ffffh 20000h to 27fffh sa5 0101xxx 64/32 50000h to 5ffffh 28000h to 2ffffh sa6 0110xxx 64/32 60000h to 6ffffh 30000h to 37fffh sa7 0111xxx 64/32 70000h to 7ffffh 38000h to 3ffffh sa8 1000xxx 64/32 80000h to 8ffffh 40000h to 47fffh sa9 1001xxx 64/32 90000h to 9ffffh 48000h to 4ffffh sa101010xxx 64/32 a0000h to affffh 50000h to 57fffh sa111011xxx 64/32 b0000h to bffffh 58000h to 5ffffh sa121100xxx 64/32 c0000h to cffffh 60000h to 67fffh sa131101xxx 64/32 d0000h to dffffh 68000h to 6ffffh bank 1 sa14111000x 16/8 e0000h to e3fffh 70000h to 71fffh sa151110 01x 32/16 e4000h to e7fffh, e8000h to ebfffh 72000h to 73fffh, 74000h to 75fffh 10x sa161110110 8/4 ec000h to edfffh 76000h to 76fffh sa171110111 8/4 ee 000h to effffh 77000h to 77fffh sa181111000 8/4 f0000h to f1fffh 78000h to 78fffh sa191111001 8/4 f2000h to f3fffh 79000h to 79fffh sa201111 01x 32/16 f4000h to f7fffh, f8000h to fbfffh 7a000h to 7bfffh, 7c000h to 7dfffh 10x sa21111111x 16/8 fc 000h to fffffh 7e000h to 7ffffh
17 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 note: the address range is a 18 : a -1 if in byte mode (byte = v il ). the address range is a 18 : a 0 if in word mode (byte = v ih ). table 7 sector address tables (mbm29dl800ba) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank 2 sa211111xxx 64/32 f0000h to fffffh 78000h to 7ffffh sa201110xxx 64/32 e0000h to effffh 70000h to 77fffh sa191101xxx 64/32 d0000h to dffffh 68000h to 6ffffh sa181100xxx 64/32 c0000h to cffffh 60000h to 67fffh sa171011xxx 64/32 b0000h to bffffh 58000h to 5ffffh sa161010xxx 64/32 a0000h to affffh 50000h to 57fffh sa151001xxx 64/32 90000h to 9ffffh 48000h to 4ffffh sa141000xxx 64/32 80000h to 8ffffh 40000h to 47fffh sa130111xxx 64/32 70000h to 7ffffh 38000h to 3ffffh sa120110xxx 64/32 60000h to 6ffffh 30000h to 37fffh sa110101xxx 64/32 50000h to 5ffffh 28000h to 2ffffh sa100100xxx 64/32 40000h to 4ffffh 20000h to 27fffh sa9 0011xxx 64/32 30000h to 3ffffh 18000h to 1ffffh sa8 0010xxx 64/32 20000h to 2ffffh 10000h to 17fffh bank 1 sa7 000111x 16/8 1c 000h to 1ffffh 0e000h to 0ffffh sa6 0001 10x 32/16 14000h to 17fffh, 18000h to 1bfffh 0a000h to 0bfffh, 0c000h to 0dfffh 01x sa5 0001001 8/4 12000h to 13fffh 09000h to 09fffh sa4 0001000 8/4 10000h to 11fffh 08000h to 08fffh sa3 0000111 8/4 0e 000h to 0ffffh 07000h to 07fffh sa2 0000110 8/4 0c000h to 0dfffh 06000h to 06fffh sa1 0000 10x 32/16 08000h to 0bfffh, 04000h to 07fffh 04000h to 05fffh, 02000h to 03fffh 01x sa0 000000x 16/8 00000h to 03fffh 00000h to 01fffh
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 18 *1: this command is valid while fast mode. *2: this command is valid while reset =v id . *3: this data "00h" is also acceptable. notes: 1. address bits a 12 to a 18 = x = h or l for all address commands except or program address (pa), sector address (sa), and bank address (ba). 2. bus operations are defined in tables 2 and 3. 3. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 16 to a 18 ) 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of write pulse. 5. spa =sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd = sector protection verify data. output 01h at protected sector addresses and output 00h at unprotected sector addresses. 6. the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 0 to a 11 byte mode: aaah or 555h to addresses a C1 and a 0 to a 11 7. both read/reset commands are functionally equivalent, resetting the device to the read mode. table 8 mbm29dl800ta/ba command definitions command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset word 1xxxhf0h byte read/reset word 3 555h aah 2aah 55h 555h f0hrard byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0hpapd byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 ba b0h erase resume 1 ba30h set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program * 1 word 2 xxxh a0hpapd byte xxxh reset from fast mode * 1 word 2 ba 90h xxxh f0h * 3 byte ba xxxh extended sector protect* 2 word 4xxxh60hspa60hspa40hspasd byte
19 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. some commands are required bank address (ba) input. when command sequences are inputed to bank being read, the commands have priority than reading. table 8 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the devices remain enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the devices reside in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. following the command write, a read cycle from address (ba)00h retrieves the manufacture code of 04h. a read cycle from address (ba)01h for 16((ba)02h for 8) returns the device code (mbm29dl800ta = 4ah and mbm29dl800ba = cbh for 8 mode; mbm29dl800ta = 224ah and mbm29dl800ba = 22cbh for 16 mode). (see tables 5.1 and 5.2.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address (ba)02h for 16 ((ba)04h for 8). scanning the sector addresses (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector. the programming verification should be performed by verify sector protection on the protected sector. (see tables 2 and 3.) the manufacture and device codes can be allowed reading from selected bank. to read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write read/reset command sequence into the register and then autoselect command should be written into the bank to be read. if the software (program code) for autoselect command is stored into the frash memory, the device and manufacture codes should be read from the other bank where is not contain the software.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 20 to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence. byte/word programming the devices are programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see table 9, hardware sequence flags.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 21 illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) figure 22 illustrates the embedded erase tm algorithm using typical command strings and bus operations.
21 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever happens later, while the command (data=30h) is latched on the rising edge of ce or we which happens first. after time-out of 50 m s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on table 8. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 s otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 m s from the rising edge of last ce or we whichever happens first will initiate the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the 50 m s time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 21). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the sector erase begins after the 50 m s time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the devices return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase in case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. figure 22 illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank addresses of sector being erasing or suspending should be set when writting the erase suspend or erase resume command.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 22 when the erase suspend command is written during the sector erase operation, the device will take a maximum of 20 m s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin will be at hi-z and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode mbm29dl800ta/ba has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address. (refer to the figure 28 extended algorithm.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to the figure 28 extended algorithm.) (3) extended sector protection in addition to normal sector protection, the mbm29dl800ta/ba has extended sector protection as extended function. this function enable to protect sector by forcing v id on reset pin and write a commnad sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins), and write extended sector protect command (60h). a sector is typically protected in 150 m s. to verify programming of the protection circuitry, the sector addresses pins (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector protect command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih .
23 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 write operation status detailed in table 9 are all the status flags that can determine the status of the bank for the current mode operation. the read operation from the bank where is not operate embedded algorithm returns a data of memory cell. these bits offer a method for determining whether a embedded algorithm is completed properly. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consectively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consectively read. this allows the user to determine which sectors are erasing and which are not. the status flag is not output from bank (non-busy bank) not executing embedded algorithm. for example, there is bank (busy bank) which is now executing embedded algorithm. when the read sequence is [1] , [2] , [3] , the dq 6 is toggling in the case of [1] and [3]. in case of [2], the data of memory cell is outputted. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in the [1] and [3]. in the erase suspend read mode, dq 2 is toggled in the [1] and [3]. in case of [2], the data of memory cell is outputted. notes: 1. successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. 2. dq 0 and dq 1 are reserve pins for future use. 3. dq 4 is fujitsu internal use only. table 9 hardware sequence flags status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle (note 1) erase suspended mode erase suspend read (erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1 (note 1) exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 24 dq 7 data polling the mbm29dl800ta/ba devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in figure 23. for programming, the data polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 100 m s, then the bank returns to read mode. once the embedded algorithm operation is close to being completed, the mbm29dl800ta/ba data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see table 9.) see figure 9 for the data polling timing specifications and diagrams. dq 6 toggle bit i the mbm29dl800ta/ba also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 m s and then stop toggling without the data having changed. in erase, the devices will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 100 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle.
25 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 the system can use dq 6 to determine whether a sector is actively erasing or is erase-suspended. when a bank is actively erasing (that is, the embedded erase algorithm is in progress), dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during the erase-suspend-program cause dq 6 to toggle. to operate toggle bit function properly, ce or oe must be high when bank address is changed. see figure 10 for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in tables 2 and 3. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the devices were incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see table 9: hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows:
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 26 for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also table 9 and figure 19. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed. note: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non- erase suspend sector address will indicate logic 1 at the dq 2 bit. ry/by ready/busy the mbm29dl800ta/ba provide a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the devices are busy with either a program or erase operation. if the output is high, the devices are ready to accept any read/ write or erase operation. when the ry/by pin is low, the devices will not accept any additional program or erase commands. if the mbm29dl800ta/ba are placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth write pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to figure 11 and 12 for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . byte/word configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29dl800ta/ba devices. when this pin is driven high, the devices operate in the word (16-bit) mode. the data is read and programmed at dq 0 to dq 15 . when this pin is driven low, the devices operate in byte (8-bit) mode. under this mode, the dq 15 /a -1 pin becomes the lowest address bit and dq 8 to dq 14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 0 to dq 7 and the dq 8 to dq 15 bits are ignored. refer to figures 13, 14 and 15 for the timing diagram. data protection the mbm29dl800ta/ba are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automatically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle (note) erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1 (note)
27 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 28 n absolute maximum ratings storage temperature .................................................................................................. C55c to + 125c ambient temperature with power applied .................................................................. C40c to +85c voltage with respect to ground all pins except a 9 , oe , reset (note 1) ................... C0.5 v to v cc +0.5 v v cc (note 1) ................................................................................................................ C0.5 v to +5.5 v a 9 , oe , and reset (note 2) ...................................................................................... C0.5 v to +13.0 v notes: 1. minimum dc voltage on input or i/o pins are C0.5 v. during voltage transitions, inputs may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins are v cc +0.5 v. during voltage transitions, outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe and reset pins are C0.5 v. during voltage transitions, a 9 , oe and reset pins may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 , oe and reset pins are +13.0 v which may positive overshoot to 14.0 v for periods of up to 20 ns. when v cc is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating ranges ambient temperature (t a ) ........................................................................................... C40c to +85c v cc supply voltages mbm29dl800ta/ba-70 ........................................................................................... +3.0 v to +3.6 v mbm29dl800ta/ba-90/-12..................................................................................... +2.7 v to +3.6 v operating ranges define those limits between which the functionality of the devices are guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. al w a ys use semiconductor d e vices within their recommended ope r ating condition r ange s . ope r ation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand.
29 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 n maximum overshoot +0.6 v ?.5 v 20 ns ?.0 v 20 ns 20 ns figure 1 maximum negative overshoot waveform v cc +0.5 v +2.0 v v cc +2.0 v 20 ns 20 ns 20 ns figure 2 maximum positive overshoot waveform 1 +13.0 v v cc +0.5 v +14.0 v 20 ns 20 ns 20 ns *: this waveform is applied for a 9 , oe, and reset. figure 3 maximum positive overshoot waveform 2
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 30 n dc characteristics notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component. 2. i cc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 300 ns. 4. applicable for only v cc applying. 5. embedded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol parameter description test conditions min. max. unit i li input leakage current v in = v ss to v cc , v cc = v cc max. C1.0 +1.0 m a i lo output leakage current v out = v ss to v cc , v cc = v cc max. C1.0 +1.0 m a i lit a 9 , oe , reset inputs leakage current v cc = v cc max. a 9 , oe , reset = 12.5 v 35 m a i cc1 v cc active current (note 1) ce = v il , oe = v ih , f=10 mhz byte 18 ma word 20 ce = v il , oe = v ih , f=5 mhz byte 8 ma word 10 i cc2 v cc active current (note 2) ce = v il , oe = v ih 35ma i cc3 v cc current (standby) v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v 5 m a i cc4 v cc current (standby, reset) v cc = v cc max., reset = v ss 0.3 v 5 m a i cc5 v cc current (automatic sleep mode) (note 3) v cc = v cc max., ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v 5a i cc6 v cc active current (note 5) (read-while-program) ce = v il , oe = v ih byte 45 ma word 45 i cc7 v cc active current (note 5) (read-while-erase) ce = v il , oe = v ih byte 45 ma word 45 i cc8 v cc active current (erase-suspend-program) ce = v il , oe = v ih 35ma v il input low level C0.5 0.6 v v ih input high level 2.0 v cc +0.3 v v id voltage for autoselect and sector protection (a 9 , oe , reset ) (note 4) 11.5 12.5 v v ol output low voltage level i ol = 4.0 ma, v cc = v cc min. 0.45 v v oh1 output high voltage level i oh = C2.0 ma, v cc = v cc min. 2.4 v v oh2 i oh = C100 m av cc C0.4 v v lko low v cc lock-out voltage 2.3 2.5 v
31 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 n ac characteristics ? read only operations characteristics note: test conditions: output load: 1 ttl gate and 30 pf (mbm29dl800ta/ba-70) 1 ttl gate and 100 pf (mbm29dl800ta/ba-90/-12) input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output:1.5 v parameter symbols description test setup -70 (note) -90 (note) -12 (note) unit jedec standard t avav t rc read cycle time min. 70 90 120 ns t avqv t acc address to output delay ce = v il oe = v il max. 70 90 120 ns t elqv t ce chip enable to output delay oe = v il max. 90 90 120 ns t glqv t oe output enable to output delay max. 30 35 50 ns t ehqz t df chip enable to output high-z max. 25 30 30 ns t ghqz t df output enable to output high-z max. 25 30 30 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min.0 0 0ns t ready reset pin low to read mode max. 20 20 20 m s t elfl t elfh ce or byte switching low or high max. 5 5 5 ns c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w notes: c l = 30 pf including jig capacitance (mbm29lv800ta/ba-90) c l = 100 pf including jig capacitance (mbm29lv800ta/ba-10/-12) figure 4 test conditions
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 32 ? write/erase/program operations (continued) parameter symbols description mbm29dl800ta/ba unit jedec standard -70 -90 -12 t avav t wc write cycle time min. 70 90 120 ns t avwl t as address setup time min. 0 0 0 ns t aso address setup time to oe low during toggle bit polling min. 15 15 15 ns t wlax t ah address hold time min. 45 45 50 ns t aht address hold time from ce or oe high during toggle bit polling min. 0 0 0 ns t dvwh t ds data setup time min. 35 45 50 ns t whdx t dh data hold time min. 0 0 0 ns t oeh output enable hold time read min. 0 0 0 ns toggle and data polling min. 10 10 10 ns t ceph ce high during toggle bit polling min. 20 20 25 ns t oeph oe high during toggle bit polling min. 20 20 25 ns t ghwl t ghwl read recover time before write min. 0 0 0 ns t ghel t ghel read recover time before write min. 0 0 0 ns t elwl t cs ce setup time min. 0 0 0 ns t wlel t ws we setup time min. 0 0 0 ns t wheh t ch ce hold time min. 0 0 0 ns t ehwh t wh we hold time min. 0 0 0 ns t wlwh t wp write pulse width min. 35 45 50 ns t eleh t cp ce pulse width min. 35 45 50 ns t whwl t wph write pulse width high min. 25 25 30 ns t ehel t cph ce pulse width high min. 25 25 30 ns t whwh1 t whwh1 byte programming operation typ. 8 8 8 s t whwh2 t whwh2 sector erase operation (note 1) typ. 1 1 1 sec t vcs v cc setup time min. 50 50 50 s t vidr rise time to v id (note 2) min. 500 500 500 ns t vlht voltage transition time (note 2) min. 4 4 4 s t wpp write pulse width (note 2) min. 100 100 100 s t oesp oe setup time to we active (note 2) min. 4 4 4 s
33 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 (continued) notes: 1. this does not include the preprogramming time. 2. this timing is for sector protection operation. parameter symbols description mbm29dl800ta/ba unit jedec standard -70 -90 -12 t csp ce setup time to we active (note 2) min. 4 4 4 s t rb recover time from ry/by min. 0 0 0 ns t rp reset pulse width min. 500 500 500 ns t rh reset hold time before read min. 200 200 200 ns t flqz byte switching low to output high-z max. 30 35 50 ns t fhqv byte switching high to output active min. 30 35 50 ns t busy program/erase valid to ry/by delay max. 90 90 90 ns t eoe delay time from embedded output enable max. 30 35 50 ns
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 34 n switching waveforms ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h ??or ? any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance ?ff?state we oe ce t acc t df t ce t oe outputs t rc addresses addresses stable high-z output valid high-z t oeh figure 5.1 ac waveforms for read operations
35 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 reset t acc t oh outputs t rc addresses addresses stable high-z output valid t rh ce t rp t rh t ce figure 5.2 ac waveforms for hardware reset/read operations
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 36 t ch t wp t whwh1 t wc t ah ce oe t rc addresses data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out figure 6 alternate we controlled program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
37 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 t cp t ds t whwh1 t wc t ah we oe addresses data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd figure 7 alternate ce controlled program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 38 v cc ce oe addresses data t wp we 555h 2aah 555h 555h 2aah sa t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h/ 30h figure 8 ac waveforms chip/sector erase operations notes: 1. sa is the sector address for sector erase. addresses = 555h (word), aaah (byte) for chip erase. 2. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
39 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 t oeh t oe t whwh1 or 2 ce oe t eoe t busy we data t df t ch t ce high-z high-z dq 7 = valid data dq 0 to dq 6 valid data dq 7 * dq 7 dq 0 to dq 6 ry/by data dq 0 to dq 6 = output flag figure 9 ac waveforms for data polling during embedded algorithm operations * : dq 7 = valid data (the device has completed the embedded operation).
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 40 t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph figure 10 ac waveforms for toggle bit i during embedded algorithm operations * : dq 6 stops toggling (the device has completed the embedded operation).
41 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 the rising edge of the last write pulse ce ry/by we t busy entire programming or erase operations figure 11 ry/by timing diagram during program/erase operations t rp reset t ready ry/by we t rb figure 12 reset /ry/by timing diagram
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 42 figure 13 timing diagram for word mode configuration ce byte t elfh t fhqv a -1 data output (dq 0 to dq 7 ) dq 15 dq 15 /a -1 dq 0 to dq 14 (dq 0 to dq 14 ) data output figure 14 timing diagram for byte mode configuration ce byte dq 15 /a -1 dq 0 to dq 14 t elfl dq 15 a -1 t flqz data output (dq 0 to dq 7 ) (dq 0 to dq 14 ) data output the falling edge of the last write signal t hold ce or we (t ah ) t set (t as ) input valid byte figure 15 byte timing diagram for write operations
43 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 t vlht sax a 18 , a 17 , a 16 a 15 , a 14 a 13 , a 12 say a 0 a 6 a 9 12 v 3 v t vlht oe 12 v 3 v t vlht t vlht t oesp t wpp t csp we ce t oe 01h data v cc a 1 t vcs figure 16 ac waveforms for sector protection sax : sector address for initial sector say : sector address for next sector note: a -1 is v il on byte mode.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 44 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period figure 17 temporary sector unprotection timing diagram figure 18 back-to-back read/write timing diagram note: dq 2 is read from the erase-suspended sector. ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note: this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2.
45 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce figure 19 dq 2 vs. dq 6 note: dq 2 is read from the erase-suspended sector.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 46 figure 20 extended sector protection timing diagram spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 150 m s (min) spay reset a 6 oe we ce data a 1 v cc a 0 add spax spax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe t wp
47 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 no yes program command sequence* (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address last address ? program address/program data start programming completed figure 21 embedded program tm algorithm embedded algorithms * : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 48 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequece (see below) data polling or toggle bit successfully completed chip erase command sequence* (address/command): individual sector/multiple sector* erase command sequence (address/command): sector address/30h sector address/30h sector address/30h erasure completed start figure 22 embedded erase tm algorithm embedded algorithms * : the sequence is applied for 16 mode. the addresses differ from 8 mode.
49 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 dq 7 = data? no no dq 7 = data? dq 5 = 1? yes yes no read (dq 0 to dq 7 ) addr. = va read (dq 0 to dq 7 ) addr. = va yes start fail pass figure 23 data polling algorithm note: dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = byte address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = any of the sector addresses within the sector not being protected during chip erase
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 50 dq 6 = toggle ? yes no dq 6 = toggle ? dq 5 = 1? yes no no yes read (dq 0 to dq 7 ) addr. = va read (dq 0 to dq 7 ) addr. = va start pass fail figure 24 toggle bit algorithm note: dq 6 is rechecked even if dq 5 = 1 because dq 6 may stop toggling at the same time as dq 5 changing to 1 . va = bank address being executed embedded algorithm.
51 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 setup sector addr. (a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id , a 6 = ce = v il , reset = v ih a 0 = v il , a 1 = v ih plscnt = 1 time out 100 m s read from sector (addr. = sa, a 0 = v il , a 1 = v ih , a 6 = v il )* remove v id from a 9 write reset command increment plscnt no yes protect another sector? data = 01h? plscnt = 25? device failed remove v id from a 9 write reset command start sector protection completed figure 25 sector protection algorithm * : a -1 is v il on byte mode.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 52 reset = v id (note 1) perform erase or program operations reset = v ih start temporary sector unprotection completed (note 2) figure 26 temporary sector unprotection algorithm notes: 1. all protected sectors are unprotected. 2. all previously protected sectors are protected once again.
53 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 figure 27 extended sector protection algorithm to sector protection yes no no plscnt = 1 no yes protection other sector start sector protection extended sector plscnt = 25? device failed remove v id from reset completed remove v id from reset write reset command write reset command reset = v id wait to 4 m s protection entry? to setup sector protection write xxxh/60h write spa/60h (a 0 = v il , a 1 = v ih , a 6 = v il ) time out 150 m s to verify sector protection write spa/40h (a 0 = v il , a 1 = v ih , a 6 = v il ) data = 01h? ? device is operating in temporary sector read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) increment plscnt setup next sector address no yes yes unprotection mode fast mode algorithm
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 54 figure 28 embedded program tm algorithm for fast mode fast mode algorithm start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify byte? no program address/program data data polling device last address ? programming completed (ba) xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode * : the sequence is applied for 16 mode. the addresses differ from 8 mode.
55 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 n erase and programming performance n tsop(i) pin capacitance note: test conditions t a = 25c, f = 1.0 mhz n fbga pin capacitance note: test conditions t a = 25c, f = 1.0 mhz parameter limits unit comments min. typ. max. sector erase time 1 10 sec excludes programming time prior to erasure word programming time 16 360 m s excludes system-level overhead byte programming time 8 300 m s chip programming time 8.4 25 sec excludes system-level overhead program/erase cycle 100,000 cycles parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 10 pf
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 56 n package dimensions c 1996 fujitsu limited f48029s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.40?.20 (.724?008) 20.00?.20 (.787?008) 19.00?.20 (.748?008) 0.10(.004) 0.50?.10 (.020?004) 0.15?.05 (.006?002) 11.50ref (.460) 0.50(.0197) typ 0.20?.10 (.008?004) 0.05(0.02)min .043 ?002 +.004 ?.05 +0.10 1.10 m 0.10(.004) (stand off) 1 24 25 48 lead no. * * 12.00?.20 (.472?008) (mounting height) (mounting height) 48-pin plastic tsop(i) (fpt-48p-m19) dimensions in mm (inches) * resin protrusion. (each side: 0.15 (.006)max) (continued) c 1996 fujitsu limited f48030s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.40?.20 (.724?008) 20.00?.20 (.787?008) 19.00?.20 (.748?008) 0.10(.004) 0.50?.10 (.020?004) 0.15?.10 (.006?002) 11.50(.460)ref 0.50(.0197) typ 0.20?.10 (.008?004) 0.05(0.02)min .043 ?002 +.004 ?.05 +0.10 1.10 m 0.10(.004) (stand off) 1 24 25 48 ead no. * * 12.00?.20(.472?008) (mounting height) (mounting height) 48-pin plastic tsop(i) (fpt-48p-m20) dimensions in mm (inches) * resin protrusion. (each side: 0.15 (.006)max)
57 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 (continued) (continued) c 1997 fujitsu limited b48002s-1c-2 9.00?.20(.354?008) 0.35?.10(.014?004) (stand off) 1.20(.047)max (mounting height) 6.00?.20 (.236?008) 0.10(.004) 0.80(.031)nom 5.60(.221) 4.00(.157) 0.40?.10 (.016?004) m 0.08(.003) 0.80(.031) nom index hgf edcba 6 5 4 3 2 1 (mounting height) 48-pin plastic fbga (bga-48p-m02) dimensions in mm (inches) note: the actual shape of corners may differ from the dimension.
mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 58 (continued) c 1998 fujitsu limited b480012s-2c-2 9.00?.20(.354?008) 0.38?.10(.015?004) (stand off) (mounting height) 6.00?.20 (.236?008) 0.10(.004) 0.80(.031)typ 5.60(.221) 4.00(.157) 48-0.45?.10 (48-.018?004) m 0.08(.003) index hgf edcba 6 5 4 3 2 1 c0.25(.010) .041 ?004 +.006 ?.10 +0.15 1.05 dimensions in mm (inches) 48-pin plastic fbga (bga-48p-m12) note: the actual shape of corners may differ from the dimension.
59 mbm29dl800ta -70/-90/-12 /mbm29dl800ba -70/-90/-12 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9904 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inhereut chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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